SOI substrate

ABSTRACT

An SOI substrate having a partial SOI structure in which a buried insulating film having a predetermined area is formed via an active layer in a part of a silicon single crystal substrate in plan view by ion-implanting elements to the part of the substrate and then applying thereto a thermal processing, wherein a thickness of a peripheral edge portion of said buried insulating film is getting thinner toward a terminal edge of said buried insulating film.

This application is a division of U.S. application Ser. No. 10/740,566,filed Dec. 22, 2003. This application claims priority of Japaneseapplication No. 2002-372898, filed Dec. 24, 2002, which is incorporatedherein by reference

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to an SOI (Silicon On Insulator)substrate and a manufacturing method thereof, and in particular, to anSOI substrate comprising a silicon substrate including in part an SOIstructure in plan view, or an SOI substrate comprising a siliconsubstrate including in part a buried insulating film formed therein, andalso to a manufacturing method thereof. Said SOI structure includes aSIMOX (Separation by IMplanted OXygen) structure.

2. Description of the Related Art

Aiming for a reduction in a manufacturing cost of a device as well as animprovement of a working speed, the SoC (System on Chip) technology hasbeen suggested for providing a mixed packaging of a logic circuit and amemory circuit on one chip. Preferably, this logic circuit may befabricated on the SOI substrate in order to reduce electric powerconsumption and improve the working speed. Further, preferably thememory circuit may be fabricated on a bulk crystal from a viewpoint of acrystal integrity. In this connection, a partial SOI (patterned SOI)structure has been invented, which allows for a bulk region to be leftin a part of the SOI substrate.

Conventionally, as an exemplary manufacturing method of the SIMOXsubstrate having the partial SOI structure, there has been known, forexample, a technique described in the Japanese Patent Laid-openPublication 5-82525.

Said technique defines such a manufacturing method in which, first ofall, a surface of a silicon single crystal substrate is partially maskedwith a silicon oxide film or the like. After that, similarly to thefabrication of a regular SIMOX substrate, oxygen ions are implanted intoa surface of the above silicon single crystal substrate, which is thensubject to a thermal processing at a high temperature. By way of this,the SIMOX substrate can be fabricated, which has a partial SOI structurewith a buried silicon oxide film formed between an active layer and abulk layer in a part of said silicon single crystal substrate, or aregion thereof having no masking applied. This manufacturing method isespecially advantageous in improving of an activity aiming for a highquality of the SIMOX substrate having a thin film of active layer.

In such a manufacturing method of the SIMOX substrate as stated aboveaccording to the prior art, however, the buried silicon oxide film isexpanded in its volume during the high temperature thermal processing,leading to a strain/stress to be induced in an interface between theburied silicon oxide film and the bulk layer. There has been a fear, inassociation with this, that a dislocation could be propagated across aregion defined by a distance of some μm from this interface (IBM,Hannon, et al., 2000 Symposium on VLSI Tech. Digest).

There is another fear remaining that if the pattern of the partial SOIstructure became highly micro-fabricated in future, the dislocation ofthe pattern could affect inversely to yield of the device.

SUMMARY OF THE INVENTION

To this end, the inventors of the present invention have devotedthemselves in an enthusiastic research and made the present inventionbased on the finding that if the thickness of a peripheral edge portionof a buried silicon oxide film formed partially in the SOI substrate ismade thinner toward a terminal edge of the buried insulating film, anamount of expansion in volume of the buried silicon oxide film in theperipheral edge portion there of during a high temperature thermalprocessing could be reduced decrementally or consecutively, to therebyreduce a strain/stress possibly induced in an interface between theburied silicon oxide film and a bulk layer and thus to inhibit saiddislocation from being induced.

An object of the present invention is to provide an SOI substrate, inwhich a strain/stress possibly induced in an interface between apartially formed buried insulating film and a bulk layer can be reducedand thus the occurrence of a dislocation resultant from saidstrain/stress can be inhibited.

Another object of the present invention is to provide a manufacturingmethod of an SOI substrate that can inhibit the occurrence ofdislocation of a partial SOI structure.

A first invention provides an SOI substrate having a partial SOIstructure in which a buried insulating film having a predetermined areais formed via an active layer in one part of a silicon single crystalsubstrate in plan view, wherein a thickness of a peripheral edge portionof said buried insulating film is getting thinner toward a terminal edgeof said buried insulating film.

The phrase that the thickness of the peripheral edge portion of theburied insulating film is getting thinner toward the terminal edge ofthe buried insulating film means, for example, a state where theperipheral edge portion of the buried insulating film exhibiting apredetermined shape in plan view is getting thinner toward the terminalend thereof in sectional view.

The number of the buried insulating film(s) to be formed in one piece ofsilicon single crystal substrate, or in other words, the number offormations of the partial SOI structure(s), may be one or may be more.

The location in which the partial SOI structure is formed may be acentral region or a peripheral region of the silicon single crystalsubstrate. Further, the shape and size of the partial SOI structure maynot be limited.

The thickness of the active layer containing the buried insulating filmformed therein when viewed in cross section may be in a range of 0.01 to0.3 μm, for example. Further, the thickness of the buried insulatingfilm in the portion excluding the peripheral edge portion having thereducing thickness, or in the portion forming a constant thickness, maybe in a range of 0.1 to 0.5 μm, for example. In the case where aplurality of partial SOI structures are formed in a piece of siliconsingle crystal substrate, each of the buried insulating films mayinclude the peripheral edge portion having the gradually reducingthickness and the thickness of respective films may be uniform or may bedifferent from one another. The latter case may be advantageous in thepoint that, for example, when the element structures are different fromone another, an optimal insulating film thickness can be achieved foreach of the elements.

In the peripheral edge portion of the buried insulating film having thereduced thickness, the thickness thereof may be reduced in steps orconsecutively. Reducing the thickness in steps means that there is aportion having the constant thickness in the middle of the portionhaving reduced thickness. Reducing the thickness consecutively meansthat, for example, the thickness thereof is reduced along a lineardiagonal line or along a curved diagonal line in a cross sectionparallel to the direction of thickness of the buried insulating film.

The size (area) of the buried insulating film may not be limited. In thecase where a plurality of partial SOI structures have been formed in onepiece of silicon single crystal substrate, the buried insulating filmsmay have the same size or different sizes, respectively.

A second invention provides an SOI substrate in accordance with thefirst invention, in which a shape of said buried insulating film iscircular, elliptic or polygonal shape in plan view.

The shape of the buried insulating film, in plan view of the SOIsubstrate with its surface (main surface) facing up may be, for example,circular, elliptic or polygonal (e.g., at least triangular orrectangular) shape. In the case where a plurality of partial SOIstructures have been formed in one piece of silicon single crystalsubstrate, the buried insulating films may have the same shape ordifferent shapes, respectively.

A third invention provides an SOI substrate in accordance with the firstinvention, in which a width of said peripheral edge portion havingreduced thickness of said buried insulating film is in a range of 10 nmto 1000 nm.

The width of the peripheral edge portion having reduced thickness isdefined, in case of a circular buried oxide film having been formed inplan view for example, by a length of the peripheral edge portion ofsaid circular insulating film measured in the radial direction from itsouter edge (across a thinned film section). This thinned film section isdefined such that, in plan view of the SOI substrate with its surfacefacing up, the insulating film in the circular shape, for example, isthinning toward its outer terminal edge. Specifically, it means that inthe peripheral edge portion having reduced thickness of the buriedinsulating film, the thickness is decreasing gradually in a directionorthogonal to a tangential line in contact with a base end of saidperipheral edge portion having reduced thickness.

In the case where a plurality of partial SOI structures have been formedin one piece of silicon single crystal substrate, the peripheral edgeportions having reduced thickness of respective buried insulating filmsmay have the same width or different widths, respectively.

Preferably, the width of the peripheral edge portion having reducedthickness of the buried insulating film may be in a range of 20 nm to500 nm. The width of the peripheral edge portion not greater than 10 nmwould not bring about any effect for inhibiting the dislocation frombeing induced. Further, although the width over 1000 nm would hardlyinduce the dislocation, the region of the peripheral edge portion havingreduced thickness of the buried insulating film would reach the deviceforming region, which could occasionally deteriorate a reliability ofthe device.

The buried insulating film may include silicon oxides, for example, asilicon dioxide or a silicon monoxide.

A fourth invention provides an SOI substrate in accordance with thethird invention, in which a shape of said buried insulating film iscircular, elliptic or polygonal shape in plan view.

A fifth invention provides a manufacturing method of an SOI substratehaving a partial SOI structure, in which a buried insulating film havinga predetermined area is formed via an active layer in a part of asilicon single crystal substrate in plan view by ion-implanting elementsto the part of the silicon single crystal substrate in plan view andthen applying thereto a thermal processing, wherein a thickness of aperipheral edge portion of said buried insulating film is gettingthinner toward a terminal edge of said buried insulating film, saidmethod characterized in comprising: a masking film preparation step forpreparing such a masking film that has an opening and is configured suchthat a thickness of said masking film in an edge portion defining andsurrounding said opening is getting thinner toward the opening; amasking step for providing said masking film over a surface of saidsilicon single crystal substrate; an ion implantation step, subsequentto said masking step, for ion-implanting said elements from above thesurface of said silicon single crystal substrate through said maskingfilm to cause said elements to be bonded with the silicon in apredetermined depth; and a thermal processing step, subsequent to saidion implantation step, for applying the thermal processing to saidsilicon single crystal substrate to thereby form the buried insulatingfilm in a location of a predetermined depth in said silicon singlecrystal substrate.

According to this manufacturing method of the SOI substrate, theelements are ion-implanted from above the surface of the silicon singlecrystal substrate through the opening of the masking film. At that time,the thickness of the masking film in its edge portion surrounding theopening is getting thinner toward the terminal end of the edge portionsurrounding the opening. Owing to this, the amount of the ionimplantation of the elements in the peripheral edge portion of saidion-implanted zone is getting lesser toward the terminal edge thereof.

During the subsequent thermal processing, the fusion or bonding of theion-implanted elements with the silicon is accelerated. Thus, the buriedinsulating film is formed partially in the silicon single crystalsubstrate. Therefore, within the silicon single crystal substrate, sucha partial SOI structure consisting of the active layer, the buriedinsulating film and the bulk layer can be fabricated. During theformation of the buried insulating film in this thermal processing, theburied insulating film will be expanded in volume and induce thestrain/stress in the interface between the buried silicon oxide film andthe bulk layer. However, the amount of ion-implantation of the elementsin the peripheral edge portion of the ion-implanted zone is gettinglesser toward the terminal edge thereof. As a result, the inducedstrain/stress is relaxed in the peripheral edge portion having reducedthickness of the buried insulating film. Consequently, the strain/stresstaking effect in the interface between the buried silicon oxide film andthe bulk layer is reduced, thereby inhibiting the dislocation from beinginduced.

During the ion-implantation, the oxygen ions may be accelerated to 30keV to 200 keV for example. The density of the ion-implantation may fallin a range of 1018 atoms/cm².

The temperature of the thermal processing may be equal to or higher than1100° C., preferably in a range of 1200° C. to 1400° C. With the aid ofthis thermal processing at the high temperature, the implantedsubstances, such as oxygen, can be reacted sufficiently with the siliconto form a buried insulating film, such as a silicon oxide film.

The material of the masking film may not be limited to specific ones.For example, it may include silicon oxides, silicon nitrides, photoresist, metallic thin films and the like.

The silicon oxide may include, for example, a silicon dioxide and asilicon monoxide.

The silicon nitride may include, for example, a 4-nitride-3-silicon.

The photo resist may include, for example, a novolac resin.

The metallic thin film may include, for example, a tungsten silicidefilm.

The size and shape of the opening formed in the masking film may bemodified appropriately in association with the size and shape of theinsulating film to be buried.

In the edge portion of the masking film surrounding the opening, or theregion having reduced thickness, in one example, the thickness thereofmay be reduced along a linear diagonal line or along a curved diagonalline in a cross section parallel to the direction of thickness of theburied insulating film. Further, there may be a portion having theconstant thickness in the middle of the portion having reducingthickness.

The method for reducing the thickness of the edge portion of the maskingfilm surrounding the opening may not be limited to specific ones. Forexample, the wet etching using an etchant suitable for the material ofthe masking film may be employed.

A sixth invention provides a manufacturing method of an SOI substrate inaccordance with the fifth invention, in which said elements are oxygen.

A seventh invention provides a manufacturing method of an SOI substratein accordance with the sixth invention, in which the thickness of themasking film in said edge portion surrounding said opening is decreasedlinearly toward said opening.

An eighth invention provides a manufacturing method of an SOI substratein accordance with the sixth invention, in which a shape of said buriedinsulating film is circular, elliptic or polygonal shape in plan view.

A ninth invention provides a manufacturing method of an SOI substrate inaccordance with the sixth invention, in which a temperature of saidthermal processing is in a range of 1200° C. to 1400° C.

A tenth invention provides a manufacturing method of an SOI substrate inaccordance with the sixth invention, in which a width of the maskingfilm in said edge portion surrounding said opening is in a range of 10nm to 1000 nm.

An eleventh invention provides a manufacturing method of an SOIsubstrate in accordance with the sixth invention, in which in saidmasking film preparation step, said opening is formed by applying a wetetching to said masking film.

A twelfth invention provides a manufacturing method of an SOI substratein accordance with the fifth invention, in which the thickness of themasking film in said edge portion surrounding said opening is decreasedlinearly toward said opening.

A thirteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the twelfth invention, in which a shape ofsaid buried insulating film is circular, elliptic or polygonal shape inplan view.

A fourteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the twelfth invention, in which atemperature of said thermal processing is in a range of 1200° C. to1400° C.

A fifteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the twelfth invention, in which a width ofthe masking film in said edge portion surrounding said opening is in arange of 10 nm to 1000 nm.

A sixteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the twelfth invention, in which in saidmasking film preparation step, said opening is formed by applying a wetetching to said masking film.

A seventeenth invention provides a manufacturing method of an SOIsubstrate in accordance with the fifth invention, in which a shape ofsaid buried insulating film is circular, elliptic or polygonal shape inplan view.

The polygonal shape may include, for example, triangular or rectangularshape.

An eighteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the seventeenth invention, in which atemperature of said thermal processing is in a range of 1200° C. to1400° C.

A nineteenth invention provides a manufacturing method of an SOIsubstrate in accordance with the seventeenth invention, in which a widthof the masking film in said edge portion surrounding said opening is ina range of 10 nm to 1000 nm.

A twentieth invention provides a manufacturing method of an SOIsubstrate in accordance with the seventeenth invention, in which in saidmasking film preparation step, said opening is formed by applying a wetetching to said masking film.

A twenty-first invention provides a manufacturing method of an SOIsubstrate in accordance with the fifth invention, in which a temperatureof said thermal processing is in a range of 1200° C. to 1400° C.

A twenty-second invention provides a manufacturing method of an SOIsubstrate in accordance with the twenty-first invention, in which awidth of the masking film in said edge portion surrounding said openingis in a range of 10 nm to 1000 nm.

A twenty-third invention provides a manufacturing method of an SOIsubstrate in accordance with the twenty-first invention, in which insaid masking film preparation step, said opening is formed by applying awet etching to said masking film.

A preferred temperature of the thermal processing is in a range of 1250to 1350° C. With the temperature lower than 1200° C., the buriedinsulating film of high quality could not be obtained. The temperaturehigher than 1400° C. may cause a slip, one of crystal defects, morefrequently.

A twenty-fourth invention provides a manufacturing method of an SOIsubstrate in accordance with the fifth invention, in which a width ofthe masking film in said edge portion surrounding said opening is in arange of 10 nm to 1000 nm.

A twenty-fifth invention provides a manufacturing method of an SOIsubstrate in accordance with the twenty-fourth invention, in which insaid masking film preparation step, said opening is formed by applying awet etching to said masking film.

A preferred width of the masking film in the edge portion surroundingthe opening is in a range of 20 nm to 500 nm. The width less than 10 nmwould not allow the formation of the insulating film having a widthsufficient for inhibiting the dislocation. Further, with the widthgreater than 1000 nm, the film-thickness-reduced region of theinsulating film could occasionally reach the device forming region,which could deteriorate a reliability of the device.

The twenty-sixth invention provides a manufacturing method of an SOIsubstrate in accordance with the fifth invention, in which in saidmasking film preparation step, said opening is formed by applying a wetetching to said masking film.

In the SOI substrate according to the present invention, since thethickness of the peripheral edge portion of the buried insulating filmformed partially (in one part of its plane in plan view) in the interiorof the silicon single crystal substrate has been made thinner toward theterminal edge of said buried insulating film, therefore the expansion involume of the buried insulating film in said thinned film section duringthe thermal processing at high temperature can be reduced. This can helpreduce the strain/stress in said thinned film section, which might beinduced in the interface between the buried insulating film and the bulklayer, thus inhibiting the occurrence of the dislocation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a)-1(d) is a flow sheet showing a manufacturing method of aSIMOX substrate (SOI substrate) according to one embodiment of thepresent invention;

FIG. 2 is an enlarged sectional view of a main part of a SIMOXsubstrate, for illustrating a level difference in the surface of theSIMOX substrate having a buried silicon oxide film whose peripheral edgeportion has not been thinned;

FIG. 3 is an enlarged sectional view of a main part of the SIMOXsubstrate, for illustrating a strain/stress distribution within theSIMOX substrate having the level difference of FIG. 2;

FIG. 4 is an enlarged sectional view of a main part of a SIMOXsubstrate, for illustrating a strain/stress distribution in the SIMOXsubstrate having a buried silicon oxide film whose peripheral edgeportion defined by a distance of 50 nm from the terminal edge thereofhas been thinned;

FIG. 5 is an enlarged sectional view of a main part of a SIMOXsubstrate, for illustrating a strain/stress distribution in the SIMOXsubstrate having a buried silicon oxide film whose peripheral edgeportion defined by a distance of 180 nm from the terminal edge thereofhas been thinned;

FIG. 6 is an enlarged sectional view of a main part of a SIMOXsubstrate, for illustrating a strain/stress distribution in the SIMOXsubstrate having a buried silicon oxide film whose peripheral edgeportion defined by a distance of 300 nm from the terminal edge thereofhas been thinned;

FIG. 7 is an enlarged sectional view of a main part of a SIMOXsubstrate, for illustrating a profile of the oxygen ion-implantationwhen the oxygen ions are implanted by using a masking film whosethickness has been varied;

FIG. 8 is a graphical representation indicating results of the SIMS(secondary ion mass spectroscopy) measurements in a profile of theoxygen ion-implantation when the oxygen ions are implanted by using amasking film whose thickness has been varied;

FIG. 9 is a plan view showing a silicon single crystal substrate with amasking film including a plurality of circular openings in a latticedesign deposited on the surface thereof;

FIG. 10 is a sectional view taken along the line S-S of FIG. 9;

FIG. 11 is a plan view of a masking film for the case where the shape ofthe buried insulating film is elliptic shape; and

FIG. 12 is a plan view showing a masking film in an example, in whichthe shape of the buried insulating film is polygonal shape.

DETAILED DESCRIPTION OF THE INVENTION

An SOI substrate according to the present invention and a manufacturingmethod thereof will now be described.

The present embodiment uses a SIMOX substrate as the SOI substrate. TheSOI substrate includes the SIMOX substrate, a bonding substrate and thelikes.

First of all, a single crystal silicon ingot is pulled up by thewell-known CZ (Czochralski) method. After that, thus obtained singlecrystal ingot is processed with block cutting, slicing, beveling,lapping, etching and surface mirror polishing, in this sequence, tothereby prepare a silicon single crystal substrate 10 having a thicknessof 725 μm and a diameter of 200 mm with one of the surfaces having beenmirror polished (FIG. 1(a)).

Subsequently, the surface of this silicon single crystal substrate 10 iscovered with a masking film 11. Specifically, the silicon single crystalsubstrate 10 is introduced into a thermal oxidation furnace toexperience an oxidative thermal processing under an oxidizing gasatmosphere at 1000° C. for 100 minutes. Through this process, themasking film 11 composed of a 0.08 μm thick silicon oxide is formed onan exposed surface of the silicon single crystal substrate 10 (FIG.1(b)). The thickness of this masking film 11 has been determined to be0.08 μm, the value greater than the thickness of 0.05 μm, which isconsidered sufficient to provide a blocking effect of the masking film11 against oxygen, with the depth of implantation of the oxygen by theion-implantation taken into account.

Subsequently, a photo resist film, which is not shown but has a largenumber of circular openings arranged in a lattice design in plan view,is coated on a top of the masking film 11 in the well-known lithographytechnique. Each region on the silicon single crystal substrate 10corresponding to each of those openings defines a region in which aburied silicon oxide film (buried insulating film) 12 is to be formedlater.

After that, this silicon single crystal substrate 10 is dipped in asolution containing 10 wt % of hydrofluoric acid at 25° C. for twominutes, so that a large number of circular openings are formed in thelattice design in the masking film 11. FIG. 9 and FIG. 10 show thiscondition. The thickness of the masking film in each edge portion 11 asurrounding the opening is getting thinner gradually (continuously)toward the opening. For each circular opening, the width of the edgeportion 11 a surrounding the opening of the masking film 11, where thethickness thereof is getting thinner, is 300 nm in a radial direction ofthe opening. Further, the thickness of the edge portion 11 a surroundingthe opening is varying linearly (thinning at a certain ratio) in a crosssection parallel to the direction of thickness of the masking film 11.It is to be noted that the thickness and material of said masking film11 or the composition and concentration of said etchant (HF solution)can be modified to thereby set any desired value for the width of theedge portion 11 a surrounding the opening.

After that, this photo resist film is removed by using a predeterminedresist stripper.

Subsequently, by using a medium current ion implanter with anaccelerating voltage of 100 keV, oxygen ions are implanted at 10¹⁸atoms/cm² into the interior of said silicon single crystal substrate 10through respective openings of the masking film 11 (FIG. 1(c)). Thedepth of the implantation of oxygen ion is about 0.5 μm.

Through this process, a large number of circular ion-implanted regions“a”, each having a predetermined area and spaced by a predeterminedinterval from each other (in the lattice design), is formed within thesilicon single crystal substrate 10. Specifically, there are a largenumber of circular ion-implanted regions forming the lattice design andnot ion-implanted regions in the silicon single crystal substrate 10 inplan view. Before the process of the ion-implantation, the thickness ofthe masking film 11 in its edge portion 11 a surrounding the opening hasbeen formed to get thinner toward the terminal edge thereof. Due tothis, the amount of implantation of the oxygen in the peripheral edgeportion of the ion-implanted region “a” within the silicon singlecrystal substrate 10 is decreased gradually toward the outer edge of theion-implanted region “a”.

Next, thus obtained silicon single crystal substrate 10 is introducedinto a thermal processing furnace, that has been held to be 700° C. inadvance, and then the temperature is increased up to 1320° C. to apply ahigh temperature annealing to the substrate 10 for ten hours (FIG.1(d)). This accelerates the fusion and bonding of the ion-implantedoxygen with the silicon leading to the precipitation of oxide (SiOx).Specifically, a large number of buried silicon oxide films, each havingthe thickness in the order of 0.3 μm, are formed in each ion-implantedregion “a”. Furthermore, the thickness of each buried silicon oxide film12 in its peripheral edge portion 12 a is getting gradually thinnertoward the terminal edge of each buried silicon oxide film 12. This isbecause the amount of the ion-implantation of oxygen in the peripheraledge portion of each ion implanted region “a” is decreasing toward theouter edge of the circular ion-implanted region “a”.

As a result, a partial SOI structure arranged in the lattice design inplan view is formed in the silicon single crystal substrate 10. The areaof the partial SOI structure is made up of three-layer structureconsisting of an active layer 13, the buried silicon oxide film 12 and abulk layer 14.

It is to be noted that during said high temperature annealing process,the strain/stress may be induced in the interface between each buriedsilicon oxide film 12 and the bulk layer 14 caused by an expansion involume of the buried silicon oxide film 12, or a difference in theamount of expansion in volume between the silicon and the silicon oxide,within the silicon single crystal substrate 10. However, since thethickness of each buried silicon oxide film 12 in its peripheral edgeportion 12 a is getting gradually thinner toward the terminal end of theburied silicon oxide film 12 as described above, the strain/stress canbe relaxed in the peripheral edge portion 12 a of each buried siliconoxide film 12. Owing to this, the occurrence of the dislocationresultant from the strain/stress can be inhibited.

Thus fabricated silicon single crystal substrate 10 having the partialSOI structure may be used, for example, in the following manner in thesubsequent device process. Specifically, in the active layer (SOIregion) 13 in the region where each buried silicon oxide film has beenformed in the silicon single crystal substrate 10, a logic circuitincluding the CMOS, for example, may be formed. In the active layer(bulk region) 13 of the silicon single crystal substrate 10 between anyadjacent SOI regions, a memory circuit such as the DRAM may be formed(again FIG. 1(d)), respectively.

In FIG. 1 through FIG. 6, reference numeral 20 designates the fabricatedSIMOX substrate.

In this connection, with reference to FIG. 2 through FIG. 6, theeffectiveness on the reduction in the strain/stress according to theillustrated embodiment was examined by executing a simulation by acalculator and an actual test.

First of all, the stress in the interface between the buried siliconoxide film and the bulk layer in a conventional SIMOX substrate wascalculated. For the formation of the buried silicon oxide film,typically the high temperature annealing process in a range of 1200° C.to 1400° C. is applied. The buried silicon oxide film is expanded in itsvolume by heat during the high temperature annealing process, so that alevel difference may be developed in the surface of the SIMOX substrate20 in the interface region between the buried silicon oxide film 12 andthe bulk layer 14, as shown in FIG. 2. FIG. 3 shows a calculation resultof the strain/stress distribution for the case of, for example, 12 nmlevel difference that has been developed in this interface region. Inthe surface of the SIMOX substrate 20, the width in the radial directionof the region “M” in which the Mises stress fell in a range of 4.9×10²MPa to 6.5×10² MPa was 886 nm in the vicinity of the interface region.

Next, in one example of the present invention, the calculation wasexecuted to determine the strain/stress for the case where the thicknessof the buried silicon oxide film 12 is reduced in its region defined bya distance of about 50 nm from the terminal edge thereof (peripheraledge portion 12 a). Similarly, in the surface of the SIMOX substrate 20,the measured width in the radial direction of the interface region “M”in which the Mises stress fell in the range of 4.9×10² MPa to 6.5×10²MPa was 614 nm (FIG. 4). It has been found from the result that theregion having the higher stress is narrowed as compared to the case ofthe buried silicon oxide film 12 shown in FIG. 3. It is considered thatthe region of critical stress inducing the dislocation is also similarlynarrowed.

Similarly, for each of the case where the region having reducedthickness (peripheral edge portion 12 a) is defined by the distance of180 nm (FIG. 5) or 300 nm (FIG. 6) from the terminal edge of the buriedsilicon oxide film 12, the width of the radial direction of theinterface region “M” in which the Mises stress fell in the range of4.9×10² MPa to 6.5×10² MPa was measured. The result showed the width ofthe interface region “M” was 179 nm for the case where the region havingreduced thickness (peripheral edge portion 12 a) is defined by thedistance of 180 nm. On the other hand, for 300 nm, the stress wasrelaxed in the interior of the SIMOX substrate 20, and the interfaceregion “M” did not emerge on the substrate surface.

Then the test for examining the effectiveness of the present inventionon the reduction in strain/stress will now be described.

First of all, the masking film 11 was formed on the surface of thesilicon single crystal substrate 10, to which the oxygenion-implantation and the high temperature thermal processing wereapplied. The results are shown in Table 1. TABLE 1 Width of thinningregion Dislocation (width of peripheral edge propagating distance region12a) (nm) (μm) Test Example 1 1000 0 Test Example 2 about 500 0 TestExample 3 about 300 about 1.0 Test Example 4 about 200 about 1.5 TestExample 5 about 80  about 3.0 Test Example 6 about 10  about 7.5Comparative   0 about 7.5 Example 1

It has been confirmed from Table 1 that as the width of the peripheraledge portion 12 a of the buried silicon oxide film 12 is gettingincreased, the distance of propagation of the dislocation developed fromthe interface between the buried silicon oxide film 12 and the bulklayer 14 is getting shorter. It has been further confirmed that, for thecase of the smaller width (shorter than 10 nm) of the peripheral edgeportion 12 a in the buried silicon oxide film 12, no inhibiting effecton the dislocation takes place. It has been also confirmed that incontrast to this, for the width of the thinning peripheral edge portion12 a over 1000 nm, almost no dislocation is induced.

Subsequently, with reference to FIG. 7 and FIG. 8, it has been confirmedby using the secondary ion mass spectroscopy (SIMS) whether or not themanufacturing method of the SIMOX substrate of the present invention hasachieved a desired oxygen ion-implantation profile, or a desireddistribution having a narrowed width of the ion-implanted region “a” ofthe oxygen which is to be formed into the buried silicon oxide film 12through the high temperature thermal processing.

A graphical representation of FIG. 8 indicates a shape of the maskingfilm 11 shown in FIG. 7 and a concentration profile of the oxygenobtained when the ion-implantation is applied to the silicon singlecrystal substrate 10 by using said masking film 11. Sections A to E ofthe graphical representation of FIG. 8 correspond to the section A to Eof FIG. 7. It can be seen that as the thickness of the masking film 11increases, the implantation width “w” of the implanted oxygen ions isreduced.

Further, the silicon single crystal substrate 10 was subjected to thehigh temperature thermal processing and then the thickness of theobtained buried silicon oxide film 12 was measured by a transmissionelectron microscope. It has been confirmed from the result that in theperipheral edge portion of the buried silicon oxide film 12, the buriedsilicon oxide film 12 is getting thinner in association with thevariation of the implantation width of the oxygen ions.

The above facts show that by employing the masking system of the presentinvention to form the partial SOI structure having a shape of the buriedsilicon oxide film whose peripheral edge portion has been tapered andthinned, a partial SOI wafer of high quality with no dislocationotherwise induced from the strain/stress in the interface region betweenthe buried silicon oxide film and the bulk layer could be obtained.

It is to be noted that FIG. 11 shows the masking film 11 used in thecase where the shape of the buried insulating film is elliptical notperfect circular. For this case also, as similarly to the aboveembodiment, the HF solution has been used and the peripheral edgeportion 11 a surrounding the opening has been formed such that thethickness thereof is getting thinner gradually.

FIG. 12 shows the masking film 11 in the example in which the buriedinsulating film is polygonal (cross-shape).

In either one of the examples, the structure allowing for the thicknessof the peripheral edge portion of the buried insulating film to getthinned gradually can be fabricated by executing the ion-implantation byusing said masking film.

1. An SOI substrate having a partial SOI structure in which a buriedinsulating film having a predetermined area is formed via an activelayer in one part of a silicon single crystal substrate in plan view,wherein a thickness of a peripheral edge portion of said buriedinsulating film is getting thinner toward a terminal edge of said buriedinsulating film.
 2. An SOI substrate in accordance with claim 1, inwhich a shape of said buried insulating film is circular, elliptic orpolygonal shape in plan view.
 3. An SOI substrate in accordance withclaim 1, in which a width of said peripheral edge portion having reducedthickness of said buried insulating film is in a range of 10 nm to 1000nm.
 4. An SOI substrate in accordance with claim 3, in which a shape ofsaid buried insulating film is circular, elliptic or polygonal shape inplan view.